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HDMP-0552 Datasheet PDF

Hewlett-Packard HDMP-0552

The HDMP-0552 is a Quad Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) and data valid detection capability included. This device minimizes part count, cost and jitter accumulation while repeating incoming signals. By using Port Bypass Circuits, hard disks may be pulled out or swapped while other disks in the array are available to the system.
Part No. HDMP-0552
Datasheet HDMP-0552 Download
Manufacturer
Hewlett-Packard
Description QUAD PORT BYPASS CIRCUIT
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HDMP-0552 datasheet page 1 preview

FEATURES

● Supports 1.0625/2.125 GBd Fibre Channel operation
● Quad PBC/CDR in one package
● CDR location determined by choice of cable input/output
● Amplitude valid detection on FM_NODE[0] input
● Data valid detection on FM_NODE[0] input – Run length violation detection – Comma detection – Configurable for both singleframe and multi-frame detection
● Speed select pin for 1 or 2 GBd operation
● Single REFCLK for 1 or 2 GBd operation
● CDR selectable via external pin
● Enable/disable equalizers on all inputs
● Enable/disable selected highspeed output drivers
● High speed LVPECL I/O
● Buffered line logic (BLL) outputs (no external bias resistors required)
● 1.1 W typical power at VCC = 3.3 V
● Advanced 0.35 µ BiCMOS technology
● 64 Pin, 10 mm, low cost plastic QFP package

APPLICATIONS

● RAID, JBOD, BTS cabinets
● 1=> 1-4 serial buffer with or without CDR

DESCRIPTION

See Figure 1 for block diagram. Port Bypass Circuits are used in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations.
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