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CD4081BD - CMOS Quad 2-Input AND Gates

Download the CD4081BD datasheet PDF. This datasheet also covers the CD4081B variant, as both devices belong to the same cmos quad 2-input and gates family and are provided as variant models within a single manufacturer datasheet.

General Description

The CD4081B consist of four AND gate circuits.

Each circuit functions as a two-input AND gate.

The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations.

Key Features

  • Wide Operating Voltage Range of 3.0V to 18.0V.
  • Maximum Input Current of 1µA at 18V over Full Package-Temperature range, 100nA at 18V and 25°C.
  • Standardized Symmetrical Output Characteristics.
  • Noise Margin 1.0V min @ 5.0V supply 2.0V min @ 10.0V supply 2.5V min @ 15.0V supply CD4081B SOP-14.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CD4081B-HTC.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number CD4081BD
Manufacturer HTC KOREA
File Size 157.46 KB
Description CMOS Quad 2-Input AND Gates
Datasheet download datasheet CD4081BD Datasheet

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Other Datasheets by HTC KOREA

Part Number Description
CD4081B CMOS Quad 2-Input AND Gates
CD4081B CMOS Quad 2-Input AND Gates
CD4081BN CMOS Quad 2-Input AND Gates

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CMOS Quad 2-Input AND Gates FEATURES • Wide Operating Voltage Range of 3.0V to 18.0V • Maximum Input Current of 1µA at 18V over Full Package-Temperature range, 100nA at 18V and 25°C • Standardized Symmetrical Output Characteristics • Noise Margin 1.0V min @ 5.0V supply 2.0V min @ 10.0V supply 2.5V min @ 15.0V supply CD4081B SOP-14 DESCRIPTION The CD4081B consist of four AND gate circuits. Each circuit functions as a two-input AND gate. The outputs are fully buffered for highest noise immunity and pattern insensitivity to output impedance variations. It operates over a recommended VDD power supply range of 3V to 15V referenced to VSS. Unused inputs must be connected to VDD, VSS, or another input. Unused outputs must be left open.