HCPL-7710 Key Features
- +5 V CMOS patibility
- 8 ns maximum pulse width distortion
- 20 ns maximum prop. delay skew
- High speed: 12 Mbd
- 40 ns maximum prop. delay
- 10 kV/µs minimum mon mode rejection
- 40°C to 100°C temperature range
- Safety and regulatory approvals UL Recognized 3750 V rms for 1 min. per UL 1577 CSA ponent Acceptance Notice #5 IEC/EN/D
- VIORM = 630 Vpeak for HCPL-7710 Option 060
- VIORM = 560 Vpeak for HCPL-0710 Option 060
