HDMP-0421 Overview
The HDMP-0421 is a Single Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR), and dual Signal Detect (SD) capability. This configuration will control jitter accumulation while repeating ining signals. Port Bypass Circuits are used to provide loops that are continuously on in hard disk arrays constructed in Fibre Channel Arbitrated Loop (FC-AL) configurations.
HDMP-0421 Key Features
- Supports ANSI X3T11 1.0625 Gbps FC-AL Loop Configuration
- Supports 802.3z 1.25 Gbps Gigabit Ethernet (GE) Rates
- Single PBC, CDR, Dual Signal Detect (SD) in a Single Package
- Bidirectional, Symmetric Bypass Capability
- CDR in Bypass Path and Loop Path
- CDR Location Determined by Wiring Configuration of Pins on PCB (Patent Pending)
- Envelope Detect on Cable Input (SD) for Both Directions
- Equalizers On All Inputs
- High Speed PECL I/Os Referenced to VCC
- Buffered Line Logic (BLL) Outputs without External Bias Resistors