HDMP-0552 Overview
The HDMP-0552 is a Quad Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) and data valid detection capability included. See Figure 1 for block diagram. This device minimizes part count, cost and jitter accumulation while repeating ining signals.
HDMP-0552 Key Features
- Supports 1.0625/2.125 GBd Fibre Channel operation
- Quad PBC/CDR in one package
- CDR location determined by choice of cable input/output
- Amplitude valid detection on FM_NODE[0] input
- Data valid detection on FM_NODE[0] input
- Run length violation detection
- ma detection
- Configurable for both singleframe and multi-frame detection
- Speed select pin for 1 or 2 GBd operation
- Single REFCLK for 1 or 2 GBd operation