HI3512 Overview
Hi3512 H.264 Encoding and Decoding Processor.
HI3512 Key Features
- ARM926EJ-S, 16 KB instruction cache, and 16 KB data cache -Embedded close coupling memory with 2 KB instruction -32-bit
- USB 2.0 OTG -MII interface ,10/100Mbit/s duplex -RTC, independent supply power
- DDR2 SDRAM interface -16 bits or 32 bits -Up to 512 MB -NOR flash interface -8 bits -2 banks, each up to 32 MB
- H.264 Main Profile@Level3.0 encoding and decoding -H.264 Baseline Profile@Level3.0 encoding and decoding -MJPEG/JPEG Bas
- Linux-based SDK -High-performance H.264 PC decoding library
- PCI V2.3 -patible with the miniPCI -Supporting the master and slave modes -UART x 3 -IR -I2C -SPI, master and slave mode
- 600 mW typical power consumption -Multiple levels of power-down modes
- 1.2 V for core -3.3 V for IO with 5 V tolerance -1.8 V for DDR2 DRAM I/O
- Maximum codec performance is 90fps@D1 or 360fps@CIF. -up to 3M pixels encoding performance with 5fps. -The bit rate cont
- 441-pin TFBGA -19 mm x 19 mm, 0.8-mm ball pitch