HD151011 Overview
Down count at the rise edge of clock (CLK), Down count at the fall edge of clock ( CLK ) Jn data is preset at the rise of clock (CLK), the fall of clock (CLK ) Clock inputs (CLK, CLK ) is CMOS level Clock inputs (CLK, CLK ) is TTL level Initialize of Q = "L" Initialize of Q = "H" H: Irrespective of condition 1. Synchronous preset ( SPE) input can set max 99 down counts.
HD151011 Key Features
- High speed operation tpd (CLK or CLK to Q) = 35 ns (typ)
- High output current Fanout of 10 LS TTL Loads
- Wide operating voltage Vcc = 2 to 6 V
- Low supply current (Ta = 25°C) Icc (Static) = 4 µA (max)
- L H PR H X
- H L SPE H L
- C/T X X H L
- Mode Generally count Synchronous preset
- Initialize of Q output Initialize of Q output Operation Description Down count at the rise edge of clock (CLK), Down cou
- Pins 18 and 19 are for function test only and should be open