HD151011 Datasheet | Hitachi Semiconductor

Features - High speed operation tpd (CLK or CLK to Q) = 35 ns (typ) - High output current Fanout of 10 LS TTL Loads - Wide operating voltage Vcc = 2 to 6 V - Low supply current (Ta = 25°C) Icc (Static) = 4 µA (max) Function Table Control Inputs CLR H X - - L H PR H X - - H L SPE H L - - - - C/T X X H L - - Mode Generally count Synchronous preset - - Initialize of Q output Initialize of Q output Operation Description Down count at the rise edge of clock (CLK), Down count at the fall edge of clock ( CLK ) Jn data is preset at the rise of clock (CLK), the fall of clock (CLK ) Clock inputs (CLK, CLK ) is CMOS level Clock inputs (CLK, CLK ) is TTL level Initialize of Q = "L" Initialize of Q = "H" H: High level L: Low level Z: Immaterial - : Irrespective of condition 1. Synchronous preset ( SPE) input can set max 99 down counts. 2. When the count value is 0, the next clock pulse presets the data to invert the output. 3. CLR and PR inputs initialize output state. 4. Clock inputs (CLK, CLK ) is selectable CMOS level (VCC = 2.0 to 6.0 V) and TTL level (VCC = 4.5 to 5.5V) (Jn, C/T, PR, CLR and SPE inputs are CMOS level) Note: Don't set data exceeding 99 to Jn. (J0: LSB, J7: MSB) Pin Arrangement CO 1 J0 2 J1 3 J2 4 J3 5 J4 6 J5 7 J6 8 J7 9 GND 10 20 VCC 19 (Test 1)- 18 (Test 2)- 17 C / T 16 CLK 15 CLK 14 Q 13 PR 12 SPE 11 CLR (Top view) - Pins 18 and 19 are for function test only and should be open. Pin Description Pin Name Input pins J0 to J7 C/T CLK, CLK SPE PR CLR Output pins CO Q Pin Description Count data input for option Level change input for CLK, CLK (CMOS level or TTL level) Clock inputs CLK : Rise edge trigger CLK : Fall edge trigger Preset input for Jn data Preset input for D-type Flip Flop (Initialize "L" at Q output) Clear input for D-type Flip Flop (Initialize "H" at Q output) Output for BCD decimal counter Output for D-type Flip Flop Absolute Maximum Ratings Item Supply voltage Input / output voltage VCC, GND current...