HD74AC195 Datasheet | Hitachi Semiconductor

Description This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear. This shift register can operate in two modes: Parallel load; Shift from Q 0 towards Q3. Parallel loading is acplished by applying the four bits of data, and taking the PE Input low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the CP input. During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the PE input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to perform as a J- K or toggle flip-flop as shown in the function table. Features - - - - - Shift Right and Parallel Load Capability J-K (D-Type) Inputs to First Stage plement Output from Last Stage Asynchronous Master Reset Outputs Source/Sink 24 m A Pin Arrangement MR 1 J 2 K 3 D0 4 D1 5 D2 6 D3 7 GND 8 (Top view) 16 VCC 15 Q0 14 Q1 13 Q2 12 Q3 11 Q3 10 CP 9 PE Logic Symbol PE J CP K MR D0 D1 D2 D3 Q3 Q0 Q1 Q2 Q3 Pin Names CP D0 to D3 PE MR J, K Q0 to Q3, Q3 Clock Pulse Input (Active Rising Edge) Parallel Data Inputs Parallel Enable Input Asynchronous Master Reset J-K or D Type Serial Inputs Outputs Timing Diagram CP MR J K PE D0 D1 D2 D3 Q0 Q1 Q2 Q3 Serial Shift Clear Load Serial Shift H L H L Mode Select-Function Table Inputs Operating Modes Asynchronous Reset Shift, Set First Stage Shift, Reset First Stage Shift, Toggle First Stage Shift, Retain First Stage Parallel Load MR L H H H H H CP X PE X H H H H L J X H L H L X K X H L L H X Dn X X X X X dn Outputs Q0 L H L q0 q0 d0 Q1 L q0 q0 q0 q0 d1 Q2 L q1 q1 q1 q1 d2 Q3 L q2 q2 q2 q2 d3 Q3 H q2 q2 q2 q2 d3 H : HIGH Voltage Level L : LOW Voltage Level X : Immaterial Lower case letters indicate the state of the referenced input (or output) one setup time prior to the LOW-to HIGH transition. : LOW-to-HIGH clock...