HD74ACT373 Datasheet | Hitachi Semiconductor

Description Diagram The HD74AC373/HD74ACT373 consists of eight latches with 3-state outputs from bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is High. When LE is Low, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is Low. When OE is High, the bus output is in the high impedance state. Features - - - - Eight Latches in a Single Package 3-State Outputs for Bus Interfacing Outputs Source/Sink 24 m A HD74AC373 has TTL-patible Inputs HD74AC373/HD74ACT373 Pin Arrangement OE 1 O0 2 D0 3 D1 4 O1 5 O2 6 D2 7 D3 8 O3 9 Gnd 10 (Top view) 20 VCC 19 O7 18 D7 17 D6 16 O6 15 O5 14 D5 13 D4 12 O4 11 LE Logic Symbol D0 D1 D2 D3 D4 D5 D6 D7 LE OE O0 O1 O2 O3 O4 O5 O6 O7 Pin Names D0 - D7 LE OE O0 - O7 Data Inputs Latch Enable Input Output Enable Input 3-State Latch Outputs HD74AC373/HD74ACT373 Truth Table Inputs OE H L L L H L Z X O0 : : : : : LE X H H L Dn X L H X Outputs On Z L H O0 High Voltage Level Low Voltage Level High Impedance Immaterial Previous O 0 before Low-to-High Transition of Clock Functional Description The HD74AC373/HD74ACT373 contains eight D-type latches with 3-state standard outputs. When the Latch Enable (LE) input is High, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is Low, the latches store the information that was present on the D inputs setup time proceding the High-to-Low transition of LE. The 3-state standard outputs are controlled by the Output Enable ( OE) input. When OE is Low, the standard outputs are in the 2-state mode. When OE is High, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram D0 D1 D2 D3 D4 D5 D6 D7 D G LE O OE O0 O1 O2 O3 O4 O5 O6 O7 Please note that this...