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HD74ALVC162834A - 18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable

General Description

The HD74ALVC162834A is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation.

Data flow from A to Y is controlled by the output enable (OE).

The device operates in the transparent mode when the latch enable (LE) is low.

Key Features

  • Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1”.
  • VCC = 2.3 V to 3.6 V.
  • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C).
  • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C).
  • High output current ±12 mA (@V CC = 3.0 V).
  • All outputs have series dumping resistors, so no external resistors are required.
  • tpd (CLK to Y) = 3.5 ns (Max) (@VCC = 3.3±0.3 V, CL = 50 pF, Ta = 0 to 85°C).
  • tpd (.

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HD74ALVC162834 18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HD74ALVC162834A 18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable ADE-205-293A (Z) 2nd. Edition November 1999 Description The HD74ALVC162834A is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode when the latch enable (LE) is low. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If the LE is high, the A data is stored in the latch/flip flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state.