HD74ALVC162834A Datasheet | Hitachi Semiconductor

18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable ADE-205-293A (Z) 2nd. Edition November 1999 Description The HD74ALVC162834A is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by the output enable (OE). The device operates in the transparent mode when the latch enable (LE) is low. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level. If the LE is high, the A data is stored in the latch/flip flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to V CC through a pullup registor; the minimum value of the registor is determined by the current sinking capability of the driver. All outputs, which are designed to sink up to 12 m A, include series dumping resistors to reduce overshoot and undershoot. Features - Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1” - VCC = 2.3 V to 3.6 V - Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) - Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) - High output current ±12 m A (@V CC = 3.0 V) - All outputs have series dumping resistors, so no external resistors are required - tpd (CLK to Y) = 3.5 ns (Max) (@VCC = 3.3±0.3 V, CL = 50 p F, Ta = 0 to 85°C) - tpd (CLK to Y) = 2.5 ns (Max) (@VCC = 3.3±0.3 V, CL = 30 p F, Ta = 0 to 85°C) Function Table Inputs OE H L L L L L H: L: X: Z: ↑: Note: LE X L L H H H CLK X X X ↑ ↑ L or H A X L H L H X Output Y Z L H L H Y0 - 1 High level Low level Immaterial High impedance Low to high transition 1. Output level before the indicated steady-state input conditions were established. Pin Arrangement NC 1 NC 2 Y1 3 GND 4 Y2 5 Y3 6 VCC 7 Y4 8 Y5 9 Y6 10 GND 11 Y7 12 Y8 13 Y9 14 Y10 15 Y11 16 Y12 17 GND 18 Y13 19 Y14 20 Y15 21 VCC 22 Y16 23 Y17 24...