HD74ALVCH162501 Overview
Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A to B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level.
HD74ALVCH162501 Key Features
- VCC = 2.3 V to 3.6 V
- Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
- Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
- High output current ±12 mA (@VCC = 3.0 V)
- Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
- All outputs have equivalent 26 Ω series resistors, so no external resistors are required
