HD74ALVCH162721 Datasheet | Hitachi Semiconductor

Description The HD74ALVCH162721’s twenty flip flops are edge triggered D-type flip flops with qualified clock storage. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs, provided that the clock enable (CLKEN ) input is low. If CLKEN is high, no data is stored. A buffered output enable ( OE) input can be used to place the twenty outputs in either a normal logic state (high or low level) or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup ponents. The output enable (OE) input does not affect the internal operation of the flip flops. Old data can be retained or new data can be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 m A, include 26 Ω resistors to reduce overshoot and undershoot. Features - VCC = 2.3 V to 3.6 V - Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) - Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) - High output current ±12 m A (@V CC = 3.0 V) - Bus hold on data inputs eliminates the need for external pullup / pulldown resistors - All outputs have equivalent 26 Ω series resistors, so no external resistors are required. Function Table Inputs OE L L L L H CLKEN H L L L X CLK X ↑ ↑ L or H X D X H L X X Q0 - 1 H L Q0 - 1 Z Output Q H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Note: 1. Output level before the indicated steady state input conditions were established. Pin Arrangement OE 1 Q1 2 Q2 3 GND 4 Q3 5 Q4 6 VCC 7 Q5 8 Q6 9 Q7 10 GND 11 Q8 12 Q9 13 Q10 14 Q11 15 Q12 16 Q13 17 GND 18 Q14 19 Q15 20 Q16 21 VCC 22 Q17 23 Q18 24 GND 25 Q19 26 Q20 27 NC 28 56...