HD74CDCF2510B Overview
The HD74CDCF2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs.
HD74CDCF2510B Key Features
- Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1” Phase-lock loop clock distribution for synch
