HD74HC174 Overview
This device contains 6 master-slave flip-flops with a mon clock and mon clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state.
HD74HC174 Key Features
- High Speed Operation: tpd (Clock to Q) = 15 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Opera
- 0.5 1.35 1.8
- 0.5 1.5 3.15 4.2
- 1.9 4.4 5.9 4.13 5.63
- Output voltage
- 4.4 4.5
- 5.9 6.0
- Input current Quiescent supply current
- 95 19 16 10 pF ns ns Clock, Clear ns Clear to Clock ns Clock to Data ns Data to Clock Clear to Q ns Clock to Q Unit MHz
- 6 30 35
