Datasheet4U Logo Datasheet4U.com

HD74HC279 Datasheet Quad. S-R Latches

Manufacturer: Hitachi Semiconductor (now Renesas)

General Description

The latch is ideally suited for use as temporary stage for binary information processing and input/output units.

When either S or R is low, output is dependent on R input.

When both inputs are high, Output is stored before the indicated steady-state input conditions were established.

Overview

HD74HC279 Quad.

S–R Latches.

Key Features

  • High Speed Operation: tpd (S to Q) = 10 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) Function Table Input S.
  • H L H L H : L : Q0 : Notes: 2 Output R H H L L Q Q0 H L H.
  • 1 High level Low level The level of Q respectively, before the indicated steady-state input conditions were establishe.