HD74HC390 Description
The HD74HC390 incorporate dual decade counters, each posed of a divide-by-two and a divide-byfive counter. The divide-by-two and divide-by-five counters can be cascaded to form dual decade, dual biquinary, or various binations up to a single divide-by-100 counter. The HD74HC390 is incremented on the high to low transition (negative edge) of the clock input, and each has an independent clear input.
HD74HC390 Key Features
- High Speed Operation: tpd (Clock A to QA) = 11 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Op
- 0.5 1.35 1.8
- 0.5 1.5 3.15 4.2
- 1.9 4.4 5.9 4.13 5.63
- Output voltage
- 4.4 4.5
- 5.9 6.0
- Input current Quiescent supply current
- 95 19 16 10 pF ns ns ns ns Clear to QA, QB, QC, QD ns Clock B to Q D ns Clock B to Q C ns Clock B to Q B ns Clock A to Q
- 80 16 14 25 5 4