HD74HC597 Overview
The HD74HC597 consists of an 8-bit storage latch feeding a parallel-in, serial-out 8-bit shift register. Both the storage register and shift register have positive-edge triggered clocks. The shift register also has direct load (from storage) and clear inputs.
HD74HC597 Key Features
- High Speed Operation: tpd (SCK to QH’) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Opera
- 1, QA = SER
- 0.5 1.35 1.8
- 0.5 1.5 3.15 4.2
- 1.9 4.4 5.9 4.13 5.63
- Output voltage
- 4.4 4.5
- 5.9 6.0
- Input current Quiescent supply current
- ns ns LCK to Data ns SCK to SA ns Data to RCK ns SER to SCK ns RCK to SCK ns ns RCK to Q H ’ ns SCK or SLoad or SCLR to
