HD74HCT688
Description
The HD74HCT688 pares bit for bit two 8-bit words and indicate whether or not they are equal. The P=Q output indicates equality when it is low. A single active low enable is provided to facilitate cascading of several packages and enable parison of words greater than 8 bits. This device is useful in memory block decoding applications, where memory block enable signals must be generated from puter address information.
Features
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- - LSTTL Output Logic Level patibility as well as CMOS Output patibility High Speed Operation: tpd (Data to P=Q) = 18 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 4.5 to 5.5 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs Data P, Q P=Q P>Q P<Q X Enable G L L L H P=Q L H H H
Pin Arrangement
G P0 Q0 P1 Q1 P2 Q2 P3 Q3
1 2 3 4 5 6 7 8 9
20 VCC 19 P=Q 18 Q7 17 P7 16 Q6 15 P6 14 Q5 13 P5 12 Q4 11 P4 (Top...
