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HM514170C - Dynamic Random Access Memory

General Description

The Hitachi HM51(S)4170C are CMOS dynamic RAM organized as 262,144-word × 16-bit.

HM51(S)4170C have realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies.

Key Features

  • Single 5 V ( ±10%) High speed.
  • Access time: 70 ns/80 ns (max) Low power dissipation.
  • Active mode: 660 mW/578 mW (max).
  • Standby mode: 11 mW (max) 1.1 mW (max) (L-version) Fast page mode capability 1024 refresh cycles: 16 ms 128 ms (L-version) 2 WE -byte control 2 variations of refresh.
  • RAS -only refresh.
  • CAS -before-RAS refresh Battery backup operation (L-version) Self refresh operation (HM51S4170C).

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Full PDF Text Transcription (Reference)

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www.DataSheet4U.com HM514170C Series HM51S4170C Series 262,144-word × 16-bit Dynamic Random Access Memory Rev. 1.0 Jul. 21, 1995 Description The Hitachi HM51(S)4170C are CMOS dynamic RAM organized as 262,144-word × 16-bit. HM51(S)4170C have realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4170C offer fast page mode as a high speed access mode. Multiplexed address input permits the HM51(S)4170C to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII. Internal refresh timer enables HM51S4170C self refresh operation.