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HM514260C - 262144-word x 16-bit Dynamic Random Access Memory

General Description

The Hitachi HM51(S)4260C is CMOS dynamic RAM organized as 262,144-word × 16-bit.

HM51(S)4260C has realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies.

Key Features

  • Single 5 V (±10%) (HM51(S)4260C-6/7/8) (±5%) (HM51(S)4260C-6R) High speed.
  • Access time: 60 ns/70 ns/80 ns (max) Low power dissipation.
  • Active mode: 825 mW/788 mW/770 mW/688 mW (max).
  • Standby mode: 11 mW (max) (HM51(S)4260C-6/7/8) 10.5 mW (max) (HM51(S)4260C-6R) 1.1 mW (max) (L-version) (HM51(S)4260C-6/7/8) 1.05 mW (max) (L-version) (HM51(S)4260C-6R) Fast page mode capability 512 refresh cycles: 8 ms 128 ms (L-version) 2 CAS -byte control 2.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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HM514260C Series HM51S4260C Series 262,144-word × 16-bit Dynamic Random Access Memory ADE-203-260A (Z) Rev. 1.0 Jun. 12, 1995 Description The Hitachi HM51(S)4260C is CMOS dynamic RAM organized as 262,144-word × 16-bit. HM51(S)4260C has realized higher density, higher performance and various functions by employing 0.8 µm CMOS process technology and some new CMOS circuit design technologies. The HM51(S)4260C offers fast page mode as a high speed access mode. Multiplexed address input permits the HM51(S)4260C to be packaged in standard 400-mil 40-pin plastic SOJ and standard 400-mil 44-pin plastic TSOPII. Internal refresh timer enables HM51S4260C self refresh operation.