Datasheet Summary
128M LVTTL interface SDRAM 100 MHz 1-Mword × 32-bit × 4-bank PC/100 SDRAM
ADE-203-1122C (Z) Rev. 1.0 May. 12 , 2000 Description
The Hitachi HM5212325FBPC is a 128-Mbit SDRAM organized as 1048576-word × 32-bit × 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 90-bump fine pitch BGA.
Features
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- Single chip wide bit solution (× 32) 3.3 V power supply Clock frequency: 100 MHz (max) LVTTL interface Extremely small foot print: 0.8 mm pitch Package: FBGA (BP-90) 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability...