HM6264B Datasheet | Hitachi Semiconductor

Description The Hitachi HM6264B is 64k-bit static RAM organized 8-kword × 8-bit. It realizes higher performance and low power consumption by 1.5 µm CMOS process technology. The device, packaged in 450 mil SOP (foot print pitch width), 600 mil plastic DIP, 300 mil plastic DIP, is available for high density mounting. Features - High speed Fast access time: 85/100 ns (max) - Low power Standby: 10 µW (typ) Operation: 15 m W (typ) (f = 1 MHz) - Single 5 V supply - pletely static memory No clock or timing strobe required - Equal access and cycle times - mon data input and output Three state output - Directly TTL patible All inputs and outputs - Battery backup operation capability HM6264B Series Ordering Information Type No. HM6264BLP-8L HM6264BLP-10L HM6264BLSP-8L HM6264BLSP-10L HM6264BLFP-8LT HM6264BLFP-10LT Access time 85 ns 100 ns 85 ns 100 ns 85 ns 100 ns Package 600-mil, 28-pin plastic DIP (DP-28) 300-mil, 28-pin plastic DIP(DP-28N) 450-mil, 28-pin plastic SOP(FP-28DA) Pin Arrangement HM6264BLP/BLSP/BLFP Series NC A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE CS2 A8 A9 A11 OE A10 CS1 I/O8 I/O7 I/O6 I/O5 I/O4 (Top view) Pin Description Pin name A0 to A12 I/O1 to I/O8 CS1 CS2 Function Address input Data input/output Chip select 1 Chip select 2 Pin name WE OE NC VCC VSS Function Write enable Output enable No connection Power supply Ground HM6264B Series Block Diagram A11 A8 A9 A7 A12 A5 A6 A4 I/O1 Input data control I/O8 Row decoder Memory array 256 × 256 VCC VSS Column I/O Column decoder A1 A2 A0 A10 A3 CS2 CS1 Timing pulse generator Read, Write control WE OE HM6264B Series Function Table WE × × H H L L CS1 H × L L L L CS2 × L H H H H OE × × H L H L Mode Not selected (power down) Not selected (power down) Output disable Read Write Write VCC current I SB , I SB1 I SB , I SB1 I CC I CC I CC I CC I/O pin High-Z High-Z High-Z Dout Din Din Ref. cycle - - - Read cycle (1)- (3)...