HN58C256A Datasheet | Hitachi Semiconductor

Description The Hitachi HN58C256A and HN58C257A are electrically erasable and programmable ROMs organized as 32768-word × 8-bit. They have realized high speed low power consumption and high reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also have a 64-byte page programming function to make their write operations faster. Features - Single 5 V supply: 5 V ±10% - Access time: 85 ns/100 ns (max) - Power dissipation  Active: 20 m W/MHz, (typ)  Standby: 110 µW (max) - On-chip latches: address, data, CE, OE, WE - Automatic byte write: 10 ms max - Automatic page write (64 bytes): 10 ms max - Ready/Busy (only the HN58C257A series) - Data polling and Toggle bit - Data protection circuit on power on/off - Conforms to JEDEC byte-wide standard - Reliable CMOS with MNOS cell technology - 105 erase/write cycles (in page mode) - 10 years data retention - Software data protection - Write protection by RES pin (only the HN58C257A series) - Industrial versions (Temperatur range: - 20 to 85˚C and - 40 to 85˚C) are also available. HN58C256A Series, HN58C257A Series Ordering Information Type No. HN58C256AP-85 HN58C256AP-10 HN58C256AFP-85 HN58C256AFP-10 HN58C256AT-85 HN58C256AT-10 HN58C257AT-85 HN58C257AT-10 Access time 85 ns 100 ns 85 ns 100 ns 85 ns 100 ns 85 ns 100 ns Package 600 mil 28-pin plastic DIP (DP-28) 400 mil 28-pin plastic SOP (FP-28D) 28-pin plastic TSOP (TFP-28DB) 8 × 14 mm2 32-pin plastic TSOP (TFP-32DA) Pin Arrangement HN58C256AP/AFP Series A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 (Top view) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 A2 A1 A0 I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 CE A10 15 16 17 18 19 20 21 22 23 24 25 26 27 28 (Top view) HN58C257AT Series A2 A1 A0 NC I/O0 I/O1 I/O2 VSS I/O3 I/O4 I/O5 I/O6 I/O7 NC CE A10 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 (Top view) 16 15 14 13 12 11 10 9 8 7 6...