DESCRIPTION
of bit 5 H8S/2319, H8S/2316, H8S/2315, and H8S/2313 added Table 5.23 I/O Port States in Each Processing State LWROD and DAOEn added to Legend. Figure 5.35(a) Port G Block Diagram (Pin PG0) Amended. Amended due to the addition of the H8S/2319 FZTAT to the product lineup. Table 7.8 A/D Conversion Characteristics Nonlinearity error, offset error, full-scale error, quantization error, and absolute accuracy amended. Added. 54 3.5 Interrupt Response Times 73 4.2.5 Bus Control Register L (BCRL) 5.13 Pin Sta
Hitachi
