FEATURES
The SuperH RISC engine employs a fixed-length 16- bit instruction set, allowing an approximately 50% reduction in program size over a 32-bit instruction set. The SH7751 Series feature the SH-4 CPU, which at the object code level is upwardly compatible with the SH-1, SH-2, and SH-3 microcomputers. The SH7751 Series have an instruction cache, an operand cache that can be switched between copy-back and write-through modes, a 4-entry fullassociative instruction TLB (table look aside buffer), and MMU (memory management unit) with 64-entry full-associative shared TLB. The SH7751 Series also feature a bus state controller (BSC) that can be directly coupled to DRAM (page/EDO) and synchronous DRAM without external circuitry. Also, because of its builtin functions, such as PCI bus controller, timers, and serial communications functions, required for multimedia and OA equipment, use of the SH7751 Series enable a dramatic reduction in system costs. The features of the SH7751 Series are summarized in table 1.1.
Hitachi
