Hitachi HD74ALVC162834
The HD74ALVC162834 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. The device operates in the transparent mode when the latch enable (LE) is low. When LE is low, the A data is latched if the clock (CLK) input is held at a high or low logic level.| Part No. | HD74ALVC162834 |
|---|---|
| Datasheet | HD74ALVC162834 Download |
| Manufacturer |  Hitachi |
| Description | 18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable |
| Buy | Stock & Price |
DESCRIPTION
Data flow from A to Y is controlled by the output enable (OE). If the LE is high, the A data is stored in the latch/flip flop on the low to high transition of CLK. When OE is high, the outputs are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to V CC through a pullup registor; the minimum value of the registor is determined by the current sinking capability of the driver. All outputs, which are designed to sink up to 12 mA, include 26 Ω resistors to reduce overshoot and undershoot.FEATURES
● Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”● VCC = 2.3 V to 3.6 V
● Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
● Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
● High output current ±12 mA (@V CC = 3.0 V)
● All outputs have equivalent 26 Ω series resistors, so no external resistors are required HD74ALVC162834 Function Table Inputs OE H L L L L L H: L: X: Z: ↑: Note: LE X L L H H H CLK X X X ↑ ↑ L or H A X L H L H X Output Y Z L H L H Y0 *1 High level Low level Immaterial High impedance Low to high transition 1.
