Hitachi HD74HC73
The flip-flop has independent data, preset, clear, and clock inputs and Q and Q outputs. The logic level present at thte data input is transferred to the output during the positive going transition to the clock pulse.| Part No. | HD74HC73 |
|---|---|
| Datasheet | HD74HC73 Download |
| Manufacturer |  Hitachi |
| Description | Dual J-K Flip-Flops (with Clear) |
| Buy | Stock & Price |
DESCRIPTION
Preset and clear are independent of the clock and accomplished by a low level at the appropriate input.FEATURES
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● High Speed Operation: tpd (Clock to Q or Q) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) Function Table Inputs Preset L H L H H H H H Note: Clear H L L H H H H H L H Clock X X X Data X X X H L X X X Outputs Q H L H* H L no change no change no change 1 Q L H H*1 L H no change no change no change 1. Q and Q will remain HIGH as long as Preset and Clear are Low, but Q and Q are unpredictable, if Preset and Clear go HIGH simultaneously. HD74HC74 Pin Arrangement 1CLR 1 1D 2 1CK 3 1PR 4 1Q 5 1Q 6 GND 7 (Top view) D CLR Q CK PR Q CK PR Q D CLR Q 14 VCC 13 2CLR 12 2D 11 2CK 10 2PR 9 2Q 8 2Q Logic Diagram (1/2) PR CLR CK D # CK CK # CK # CK CK CK CK CK # CK # CK Q Q 2 HD74HC74 DC Characteristics Ta = 25°C I...
