HD74HCT623 Datasheet PDF

DESCRIPTION

This octal transceiver is designed for asynchronous two-way communication between data buses. The control function implementation allows for maximum flexibility in timng. This device allows data transmission from A bus to the B bus or from the B bus to the A bus depending upon the logic levels at the enable inputs (GBA and GAB). The enable inputs can be used to disable the device so that the buses are affectively isolated. The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of GBA and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16 in all) will remain at their last states. The 8-bit codes appearing on the two sets of buses will be identical for

FEATURES

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● LSTTL Output Logic Level Compatibility as well as CMOS Output Compatibility High Speed O...