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HN58C257A - 256k EEPROM (32-kword x 8-bit) Ready/Busy and RES function

Download the HN58C257A datasheet PDF. This datasheet also covers the HN58C256A variant, as both devices belong to the same 256k eeprom (32-kword x 8-bit) ready/busy and res function family and are provided as variant models within a single manufacturer datasheet.

General Description

The Hitachi HN58C256A and HN58C257A are electrically erasable and programmable ROMs organized as 32768-word × 8-bit.

They have realized high speed low power consumption and high reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology.

Key Features

  • Single 5 V supply: 5 V ±10%.
  • Access time: 85 ns/100 ns (max).
  • Power dissipation  Active: 20 mW/MHz, (typ)  Standby: 110 µW (max).
  • On-chip latches: address, data, CE, OE, WE.
  • Automatic byte write: 10 ms max.
  • Automatic page write (64 bytes): 10 ms max.
  • Ready/Busy (only the HN58C257A series).
  • Data polling and Toggle bit.
  • Data protection circuit on power on/off.
  • Conforms to JEDEC byte-wide standard.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HN58C256A_HitachiSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HN58C256A Series HN58C257A Series 256k EEPROM (32-kword × 8-bit) Ready/Busy and RES function (HN58C257A) ADE-203-410D (Z) Rev. 4.0 Oct. 24, 1997 Description The Hitachi HN58C256A and HN58C257A are electrically erasable and programmable ROMs organized as 32768-word × 8-bit. They have realized high speed low power consumption and high reliability by employing advanced MNOS memory technology and CMOS process and circuitry technology. They also have a 64-byte page programming function to make their write operations faster.