74173 Datasheet | Hitachi Semiconductor

Description The four D type Flip-Flops operate synchronously from a mon clock. The 3-state outputs allow the device to be used in bus organized systems. The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level. The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. Clearing is enabled by taking the clear input to a logic high level. The data outputs change state on the positive going edge of the clock. Features - - - - - High Speed Operation: tpd (Clock to Q) = 14 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs Data Enable Clear H L L L L L Clock X L G1 X X H X L L G2 X X X H L L Data D X X X X L H Output Q L Q0 Q0 Q0 L H Note: When either M or N (or both) is (are) high the output is disabled to the high-impedance state; however sequential operation of the flip-flops is not affected. HD74HC173 Pin Arrangement Output Control M 1 N 2 1Q 3 2Q 4 Output Control Clear 1Q 2Q 3Q 4Q 1D 2D 3D 4D 16 VCC 15 Clear 14 1D 13 2D 12 3D 11 4D 10 G2 9 G1 Data Enable Input Data Input Output 3Q 5 4Q 6 Clock 7 GND 8 CK Data Enable (Top view) Absolute Maximum Ratings Item Supply voltage range Input voltage Output voltage DC current drain per pin DC current drain per VCC, GND DC input diode current DC output diode current Power dissipation per package Storage temperature Symbol VCC VIN VOUT I OUT I CC, I GND I IK I OK PT Tstg Rating - 0.5 to +7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 ±35 ±75 ±20 ±20 500 - 65 to +150 Unit V V V m A m A m A m A m W °C HD74HC173 Block Diagram 1D VCC 1Q 2D VCC 2Q 3D VCC...