HCD61203U Datasheet | Hitachi Semiconductor

Description The HD61203U is a mon signal driver for dot matrix liquid crystal graphic display systems. It generates the timing signals (switch signal to convert LCD waveform to AC, frame synchronous signal) and supplies them to the column driver to control display. It provides 64 driver output lines and the impedance is low enough to drive a large screen. As the HD61203U is produced by a CMOS process, it is fit for use in portable battery-driven equipment utilizing the liquid crystal display’s low power consumption. The user can easily construct a dot matrix liquid crystal graphic display system by bining the HD61203U and the column (segment) driver HD61202U. Features - - - - - Dot matrix liquid crystal graphic display mon driver with low impedance Low impedance: 1.5 kΩ max Internal liquid crystal display driver circuit: 64 circuits Internal dynamic display timing generator circuit Display duty cycle  When used with the column driver HD61202U: 1/48, 1/64, 1/96, 1/128  When used with the controller HD61830: Selectable out of 1/32 to 1/128 Low power dissipation: During displays: 5 m W Power supplies: VCC: 2.7~5.5V Power supply voltage for liquid crystal display drive: 8V to 16V CMOS process 100-pin plastic QFP, 100-pin plastic TQFP, chip - - - - - 1 HD61203U Ordering Information Type No. HD61203UFS HD61203UTE HCD61203U Package 100-pin plastic QFP (FP-100A) 100-pin thin plastic QFP (TFP-100B) Chip HD61203U Pin Arrangement X23 X24 X25 X26 X27 X28 X29 X30 X31 X32 X33 X34 X35 X36 X37 X38 X39 X40 X41 X42 X22 X21 X20 X19 X18 X17 X16 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 VEE V6L V5L V2L V1L VCC DL FS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 HD61203UFS (FP-100A) DS1 DS2 C NC R NC CR STB SHL GND NC M/S ø2 ø1 NC FRM M NC FCS DR 31 32 33 34 35 36 37 38 39 40 41 42...