HD74AC123A Datasheet | Hitachi Semiconductor

Description Each half of the HD74AC123A features retriggerable capability, plementary dc level triggering and overriding Direct Clear. When a circuit is in the quasi-stable (delay) state, another trigger applied to the inputs (per the Truth Table) will cause the delay period to start again, without disturbing the outputs. By repeating this process, the output pulse period (Q High, Q Low) can be made as long as desired. Alternatively, a delay period can be terminated at any time by a Low signal on C D, which also inhibits triggering. An internal connection from C D to the input gate makes it possible to trigger the circuit by a positive-going signal on C D, as shown in the Truth Table. For timing capacitor values greater than 1000 p F, the output pulse width is defined as follows. Where tw is in ns, RX is in k and C tw = RXCX X is in p F. Feature - Outputs Source/Sink 24 m A Pin Arrangement A1 1 B1 2 CD1 3 Q1 4 Q2 5 CX2 6 RX2CX2 7 GND 8 (Top view) 16 VCC 15 RX1CX1 14 CX1 13 Q1 12 Q2 11 CD2 10 B2 9 A2 Logic Symbol 7 6 (15) (14) RXCX CX Q 9(1) A 10(2) B Q CD 12(4) 5(13) 11 (3) VCC = Pin16 GND = Pin8 Pin Names A1, A 2 B 1, B 2 C D1, CD2 Q1, Q2 Q1, Q 2 Trigger Inputs (Active Falling Edge) Trigger Inputs (Active Rising Edge) Direct Clear Inputs (Active Low) Positive Pulse Outputs Negative Pulse Outputs Triggering Truth Table Inputs A X B X L H H L L H : L : X : : : H High Voltage Level Low Voltage Level Immaterial Low-to-High Transition High-to-Low Transition CD L X H X H Response No trigger No trigger Trigger No trigger Trigger Trigger DC Characteristics (unless otherwise specified) Item Maximum quiescent supply current Maximum quiescent supply current Symbol I CC I CC Max 80 8.0 Unit µA µA Condition VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C AC Characteristics: HD74AC123A Ta = +25°C CL = 50 p F Item Propagation delay A or B to Q Propagation delay A or B to Q Propagation...