HD74AC166 Datasheet | Hitachi Semiconductor

Description The HD74AC166/HD74ACT166 is an 8-bit, serial or parallel-in, serial-out shift register using edge triggered D-type flip-flops. Serial and parallel entry are synchronous, with state changes initiated by the rising edge of the clock. An asynchronous Master Reset overrides other inputs and clears all flip-flops. The circuit can be clocked from two sources or one CP input can be used to trigger the other. Features - Outputs Source/Sink 24 m A - HD74ACT166 has TTL-patible Inputs Pin Arrangement DS 1 P0 2 P1 3 P2 4 P3 5 CP2 6 CP1 7 GND 8 (Top view) 16 VCC 15 PE 14 P7 13 Q7 12 P6 11 P5 10 P4 9 MR HD74AC166/HD74ACT166 Logic Symbol 15 2 3 4 5 10 11 12 14 PE P0 P1 P2 P3 P4 P5 P6 P7 1 7 6 1 2 DS CP MR Q7 13 VCC=Pin16 GND=Pin8 Pin Names CP1, CP2 DS PE P 0 to P7 MR Q7 Clock Pulse Inputs (Active Rising Edge) Serial Data Input Parallel Enable Input (Active Low) Parallel Data Inputs Asynchronous Master Reset Input (Active Low) Last Stage Output Functional Description Operation is synchronous (except for Master Reset) and state changes are initiated by the rising edge of either clock input if the other clock input is Low. When one of the clock inputs is used as an active High clock inhibt, it should attain the High state while the other clock is still in the High state following the previous operation. When the Parallel Enable ( PE ) input is Low, data is loaded into the register from the Parallel Data (P0 to P7) inputs on the next rising edge of the clock. When PE is High, information is shifted from the Serial Data (DS) input to Q0 and all data in the register is shifted one bit position (i.e., Q0 → Q1, Q1 → Q2, etc.) on the rising edge of the clock. HD74AC166/HD74ACT166 Truth Table Inputs Parallel MR L H H H H H H : L : X : : PE X X L H H X CP 2 X L L L L H CP 1 X L DS X X X H L X P0 to P7 X X a - - - h X X X Internal Outputs Q0 L QA0 a H L QA0 Q6 L QB0 b QAn QAn QB0 Output Q7 L QH0 h QGn QGn QH0 High Voltage Level Low Voltage Level Immaterial...