HD74AC174 Datasheet | Hitachi Semiconductor

Description The HD74AC174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the Low-to-High clock transition. The device has a Master Reset to simultaneously clear all flip-flops. Feature - Outputs Source/Sink 24 m A Pin Arrangement MR 1 Q0 2 D0 3 D1 4 Q1 5 D2 6 Q2 7 GND 8 (Top view) 16 VCC 15 Q5 14 D5 13 D4 12 Q4 11 D3 10 Q3 9 CP Logic Symbol D0 D1 D2 CP MR D3 D4 D5 Q0 Q1 Q2 Q3 Q4 Q5 Pin Names D0 to D5 CP MR Q0 to Q5 Data Inputs Clock Pulse Input Master Reset Input Outputs Functional Description The HD74AC174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs. The Clock (CP) and Master Reset (MR ) are mon to all flip-flops. Each D input’s state is transferred to the corresponding flip-flops’s output following the Low-to-High Clock (CP) transition. A Low input to the Master Reset (MR ) will force all outputs Low independent of Clock or Data inputs. The HD74AC174 is useful for applications where the true output only is required and the Clock and Master Reset are mon to all storage elements. Truth Table Inputs MR L H H H H : L : X : : L High Voltage Level Low Voltage Level Immaterial Low-to-High Transition of Clock CP X D X H L X Output Q L H L Q Logic Diagram MR CP D5 D4 D3 D2 D1 D0 CP CD CP CD CP CD CP CD CP CD CP...