HD74AC194 Datasheet | Hitachi Semiconductor

Description This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, operating mode control inputs, and a direct overriding clear line. The register has four destinct modes of operation: parallel (broadside) load, shift right (in the direction Q 0 toward Q3); shift left; inhibit clock (do nothing). Synchronous parallel loading is acplished by applying the four bits of data and taking both mode control inputs, S 0 and S 1, high. The data are loaded into their respective flip-flops and appear at the output after the positive transition of the clock input. During loading, serial data flow is inhibited. Shift right is acplished synchronously with the rising edge of the clock pulse when S0 is high and S1 is low. Serial date for this mode is entered at the shift right data input. When S 0 is low and S1 is high, data shifts left synchronously and new data is entered at the shifts left serial input. Clocking of the flip-flops is inhibited when both mode control inputs are low. The mode control inputs should be changed only when the clock input is high. Features - Asynchronous Master Reset - Hole (Do Nothing) Mode - Outputs Source/Sink 24 m A Pin Arrangement MR 1 DSR 2 P0 3 P1 4 P2 5 P3 6 DSL 7 GND 8 (Top view) 16 VCC 15 Q0 14 Q1 13 Q2 12 Q3 11 CP 10 S1 9 S0 Logic Symbol DSR P0 S0 S1 CP MR Q0 P1 P2 P3 Q1 Q2 Q3 Pin Names S 0, S 1 P 0 to P3 DSR DSL CP MR Q0 to Q3 Mode Control Inputs Parallel Data Inputs Serial Data Input (Shift Right) Serial Data Input (Shift Left) Clock Pulse Input (Active Rising Edge) Asynchronous Master Reset Input (Active LOW) Parallel Outputs Logic Diagram DSL P3 P2 P1 P0 DSR S0 S1 D C C Q CL CL D C C Q CL CL D C C Q CL CL D C C Q CL CL CP MR Q3 Q2 Q1 Q0 Mode Select Table Inputs Operating Mode Reset Hold Shift Left MR L H H H Shift...