HD74AC4024 Datasheet | Hitachi Semiconductor

Description The HD74AC4024 is a 4-stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input. Feature - Outputs Source/Sink 24 m A Pin Arrangement Clock Reset 13 NC Q7 12 Q1 Q6 11 Q2 Q5 10 NC Q4 6 7 9 8 Q3 (Top view) Logic Symbol Q7 Q1 Q6 Q2 Q5 Q4 Q3 Pin Names Clock Reset Q1 to Q7 Clock Input (Active Falling Edge) Master Reset Input Outputs Function Table Clock L L H H Reset L H L H L H L H H : L : High voltage level Low voltage level : Low-to-High Clock Transition : High-to-Low Clock Transition Outputs State No change All outputs are low No change All outputs are low No change All outputs are low Advance to next state All outputs are low Logic...