HD74AC539 Datasheet | Hitachi Semiconductor

Description The HD74AC539 contains two inpedendent decoders. Each accepts two Address (A 0, A1) input signals and decodes them to select one of four mutually exclusive outputs. A polarity control input (P) determines whether the outputs are active HIGH (P = L) or active LOW (P = H). An active LOW input Enable (E) is available for data demultiplexing; data is routed to the selected output in non-inverted form in the active LOW mode or in inverted form in the active HIGH mode. A HIGH signal on the active LOW Output Enable ( OE) input forces the 3-state outputs to the high impedance state. Feature - Outputs Source/Sink 24 m A Pin Arrangement O2b 1 O1b 2 O0b 3 Pb 4 OEb 5 A0a 6 A1a 7 O3a 8 O2a 9 GND 10 (Top view) 20 VCC 19 O3b 18 A1b 17 A0b 16 Eb 15 Ea 14 OEa 13 Pa 12 O0d 11 O1a Logic Symbol A0 A1 E A0 A1 DECODER a OE O0 O1 O2 O3 OE DECODER b O0 O1 O2 O3 Pin Names A0a to A1a A0b to A1b Ea - Eb OEa , OEb P a, P b O0a to O3a O0b to O3b Side A Address Inputs Side B Address Inputs Enable Inputs (Active LOW) Output Enable Inputs (Active LOW) Polarity Control Inputs Side A 3-State Outputs Side B 3-State Outputs Truth Table Inputs Function High impedance Disable Active HIGH output (P = L) OE H L L L L L Active LOW output (P = H) L L L L H L X Z : : : : High Voltage Level Low Voltage Level Immaterial High Impedance E X H L L L L L L L L A1 X X L L H H L L H H A0 X X L H L H L H L H Outputs O0 Z On = P H L L L L H H H L H L L H L H H L L H L H H L H L L L H H H H L O1 Z O2 Z O3 Z Logic Diagram (one half shown) A1 A0 OE O0 O1 O2 O3 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. DC Characteristics (unless otherwise specified) Item Maximum quiescent supply current Maximum quiescent supply current Symbol I CC I CC Max 80 8.0 Unit µA µA Condition VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case VIN = VCC or ground, VCC =...