HD74AC74 Datasheet | Hitachi Semiconductor

Description The HD74AC74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and plementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Features Asynchronous Inputs: Low input to SD (Set) sets Q to High level Low input to CD (Clear) sets Q to Low level Clear and Set are independent of clock Simultaneous Low on CD and SD makes both Q and Q High - Outputs Source/Sink 24 m A Pin Arrangement CD1 1 D1 2 CP1 3 SD1 4 Q1 5 Q1 6 GND 7 (Top view) D2 CD2 CP2 SD2 CP1 D1 SD1 CD1 14 VCC 13 CD2 12 D2 11 CP2 10 SD2 9 Q2 8 Q2 Q 1 Q1 Q 2 Q2 Logic Symbol SD1 D1 CP1 Q1 Q1 D2 SD2 Q2 CP2 Q2 CD1 CD2 Pin Names D1, D2 CP1, CP2 C D1, CD2 S D1, SD2 Q1, Q1, Q2, Q 2 Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs Truth Table (Each Half) Inputs SD L H L H H H H L X : : : : Q0 (Q0) : CD H L L H H H High Voltage Level Low Voltage Level Immaterial Low-to-High Clock Transition Previous Q (Q) before Low-to-High Transition of Clock L CP X X X D X X X H L X Outputs Q H L H H L Q0 Q L H H L H Q0 Logic Diagram D CP CD Please note that this diagram is provised only for the understanding of logic operations and should not be used to estimate propagation delays. DC Characteristics (unless otherwise specified) Item Maximum quiescent supply current Maximum quiescent supply current Symbol I CC I CC Max 40 4.0 Unit µA µA Condition VIN = VCC or ground, VCC = 5.5 V, Ta = Worst case VIN = VCC or ground, VCC = 5.5 V, Ta = 25°C AC Characteristics Ta = +25°C CL = 50 p F Item Maximum clock frequency...