HD74ACT161 Datasheet | Hitachi Semiconductor

Description The HD74ACT161 and HD74ACT163 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The HD74ACT161 have an asynchronous Master Reset input that overrides all other inputs and forces the outputs Low. The HD74ACT163 has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. Features - - - - - Synchronous Counting and Loading High-Speed Synchronous Expansion Typical Count Rate of 125 MHz Outputs Source/Sink 24 m A HD74ACT161 and HD74ACT163 have TTL-patible Inputs HD74ACT161/HD74ACT163 Pin Arrangement - R 1 CP 2 P0 3 P1 4 P2 5 P3 6 CEP 7 GND 8 (Top view) 16 VCC 15 TC 14 Q0 13 Q1 12 Q2 11 Q3 10 CET 9 PE Logic Symbol PE P0 P1 P2 P3 CEP CET CP - R Q0 Q1 Q2 Q3 - - MR for HD74ACT161 - SR for HD74AC163/HD74ACT163 TC HD74ACT161/HD74ACT163 Pin Names CEP CET CP MR (HD74ACT161) SR (HD74ACT163/HD74ACT163) P 0 to P3 PE Q0 to Q3 TC Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Asynchronous Master Reset Input Synchronous Reset Input Parallel Data Inputs Parallel Enable Input Flip-Flop Outputs Terminal Count Output Functional Description The HD74ACT161 and HD74ACT163 count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the HD74ACT161) occur as a reset of, and synchronous with, the Low-to-High transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset (HD74ACT161), synchronous reset (HD74ACT163), parallel load, countup and hold. Five control inputs - Master Reste (MR, HD74ACT161),...