HD74ACT165 Datasheet | Hitachi Semiconductor

Description This 8-bit serial shift register shifts data from Q A to QH when clocked, Parallel inputs to each stage are enabled by a low level at the Shift/Load Input. Also included is a gated clock input and a plementary output from the eighth bit. Clocking is acplished through a 2-input NOR gate permitting one input to be used as a clock inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with the Shift/Load input high enables the other clock input. Data transfer occurs on the positive going edge of the clock. Parallel loading is inhibited as long as the Shift/Load input is high. When taken low, data at the parallel inputs is loaded directly into the register independent of the state of the clock. Features - Outputs Source/Sink 24 m A - HD74ACT165 has TTL-patible Inputs HD74AC165/HD74ACT165 Pin Arrangement SL 1 CP 2 E 3 Parallel Inputs F 4 G 5 H 6 QH 7 GND 8 (Top view) 16 VCC Clock 15 Inhibit 14 D 13 C 12 B 11 A 10 SI 9 QH Parallel Inputs Logic Symbol 15 11 12 13 14 3 4 5 6 1 2 10 Clock Inhibit SL CP SI Pin Names A to H SI CP SL Clock Inhibit QH, QH Parallel Inputs Serial Input Clock Input Shift Load Clock Inhibit Outputs HD74AC165/HD74ACT165 Truth Table Inputs Clock SL L H H H H H : L : X : : Inhibit X L L L H X CP X L SI X X H L X Parallel A - - - - - - H a - - - - - - h X X X X Internal Outputs QA a QAD H L QAD QB b QBO QAn QAn QBO Outputs QH h QHO QGn QCn QHO High Voltage Level Low Voltage Level Immaterial Low-to-High Clock Transition HD74AC165/HD74ACT165 Logic Diagram Parallel Inputs A B C D E F G H Preset QA S Clock QA R Clear Preset QB S Clock QB R Clear Preset QC S Clock QC R Clear Preset QD S Clock QD R Clear Preset QE S Clock QE R Clear Preset QF S Clock QF R Clear Preset QG S Clock QG R Clear Preset QH S Clock QH R Clear Output QH Output...