HD74ALVC16835 Datasheet | Hitachi Semiconductor

Description The HD74ALVC16835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by output enable (OE). The device operates in the transparent mode when the latch enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A data is stored in the latch/flip flop on the low to high transition of the CLK. When OE is high, the outputs are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to V CC through a pullup registor; the minimum value of the registor is determined by the current sinking capability of the driver. Features - Meets “PC SDRAM registered DIMM design support document, Rev. 1.2” - VCC = 2.3 V to 3.6 V - Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) - Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) - High output current ±24 m A (@V CC = 3.0 V) Function Table Inputs OE H L L L L L L H: L: X: Z: ↑: Notes: LE X H H L L L L CLK X X X ↑ ↑ H L A X L H L H X X Output Y Z L H L H Y0 - 1 Y0 - 2 High level Low level Immaterial High impedance Low to high transition 1. Output level before the indicated steady-state input conditions were established, provided that CLK was high before LE went low. 2. Output level before the indicated steady-state input conditions were established. Pin Arrangement NC 1 NC 2 Y1 3 GND 4 Y2 5 Y3 6 VCC 7 Y4 8 Y5 9 Y6 10 GND 11 Y7 12 Y8 13 Y9 14 Y10 15 Y11 16 Y12 17 GND 18 Y13 19 Y14 20 Y15 21 VCC 22 Y16 23 Y17 24 GND 25 Y18 26 OE 27 LE 28 (Top view) 56 GND 55 NC 54 A1 53 GND 52 A2 51 A3 50 VCC 49 A4 48 A5 47 A6 46 GND 45 A7 44 A8 43 A9 42 A10 41 A11 40 A12 39 GND 38 A13 37 A14 36 A15 35 VCC 34 A16 33 A17 32 GND 31 A18 30 CLK 29 GND Absolute Maximum Ratings Item Supply voltage range Input voltage range - 1 - 1, 2 Symbol VCC VI VO I IK I OK IO I CC or IGND PT Tstg Ratings - 0.5...