HD74ALVCH162374 Datasheet | Hitachi Semiconductor

Description The HD74ALVCH162374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip flops or one 16-bit flip flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip flop take on the logic levels set up at the data (D) inputs. The output enable ( OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup ponents. OE does not affect internal operations of the flip flops. Old data can be retained or new data can be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to 12 m A, include 26 Ω resistors to reduce overshoot and undershoot. Features - VCC = 2.3 V to 3.6 V - Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) - Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) - High output current ±12 m A (@VCC = 3.0 V) - Bus hold on data inputs eliminates the need for external pullup / pulldown resistors - All outputs have equivalent 26 Ω series resistors, so no external resistors are required. Function Table Inputs OE L L L H CLK ↑ ↑ H or L X D H L X X H L Q0 - 1 Z Output Q H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Note: 1. Output level before the indicated steady state input conditions were established. Pin Arrangement 1OE 1 1Q1 2 1Q2 3 GND 4 1Q3 5 1Q4 6 V CC 7 1Q5 8 1Q6 9 GND 10 1Q7 11 1Q8 12 2Q1 13 2Q2 14 GND 15 2Q3 16 2Q4 17 V CC 18 2Q5 19 2Q6 20 GND 21 2Q7 22 2Q8 23 2OE 24 48 1CLK 47 1D1 46 1D2 45 GND...