HD74ALVCH16820 Datasheet | Hitachi Semiconductor

Description The flip flops of the HD74ALVCH16820 are edge triggered D-type flip flops. On the positive transition of the clock (CLK) input, the device provides true data at the Q outputs. A buffered output enable (OE) input can be used to place the ten outputs in either a normal logic state (high or low logic level) or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high impedance state and increased drive provide the capability to drive bus lines without need for interface or pullup ponents. OE input does not affect the internal operation of the flip flops. Old data can be retained or new data can be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Features - VCC = 2.3 V to 3.6 V - Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) - Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) - High output current ±24 m A (@V CC = 3.0 V) - Bus hold on data inputs eliminates the need for external pullup / pulldown resistors Function Table Inputs OEn - 2 L L L H CLK ↑ ↑ L X D H L X X H L Q0 - 1 Z Output Qn - 1 H : High level L : Low level X : Immaterial Z : High impedance ↑ : Low to high transition Notes: 1. Output level before the indicated steady state input conditions were established. 2. n = 1, 2 Pin Arrangement 1OE 1 1Q1 2 1Q2 3 GND 4 2Q1 5 2Q2 6 VCC 7 3Q1 8 3Q2 9 4Q1 10 GND 11 4Q2 12 5Q1 13 5Q2 14 6Q1 15 6Q2 16 7Q1 17 GND 18 7Q2 19 8Q1 20 8Q2 21 VCC 22 9Q1 23 9Q2 24 GND 25 10Q1 26 10Q2 27 2OE 28 56 CLK 55 D1 54 NC 53 GND 52 D2 51 NC 50 VCC 49 D3 48 NC 47 D4 46 GND 45 NC 44 D5 43 NC 42 D6 41 NC 40 D7 39 GND 38 NC 37 D8 36 NC 35 VCC 34 D9 33 NC 32 GND 31 D10 30 NC 29 NC (Top view) Absolute Maximum Ratings Item Supply voltage Input voltage - 1 - 1, 2 Symbol VCC VI VO I IK I OK IO I CC or IGND PT Tstg Ratings - 0.5 to 4.6 -...