HD74HC107 Datasheet | Hitachi Semiconductor

Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and acplished by a low level on the input. Features - - - - - High Speed Operation: tpd (Clock to Q) = 19 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) Function Table Inputs Clear L H H H H H H H L H Clock X J X L L H H X X X K X L H L H X X X Output Q L No change L H Toggle No change No change No change H L Q H Pin Arrangement 1J 1Q 1Q 1K 2Q 2Q GND 1 2 Q 3 4 5 6 7 (Top View) Q Q K CK CLR J Q 14 13 12 11 10 9 8 VCC 1CLR 1CK 2K 2CLR 2CK 2J CLR J CK K Block Diagram (1/2) CLR J K CK CK CK CK CK CK Q Q CK CK DC Characteristics Ta = 25°C Item Input voltage Symbol VIH Ta = - 40 to +85°C Max - - - 0.5 1.35 1.8 - - - - - 0.1 0.1 0.1 0.33 0.33 ±1.0 20 µA µA I OL = 4 m A I OL = 5.2 m A Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA V I OH = - 4 m A I OH = - 5.2 m A Vin = VIH or VIL I OL = 20 µA V Vin = VIH or VIL I OH = - 20 µA V Unit V Test Conditions VCC (V) Min Typ Max Min 2.0 4.5 6.0 1.5 - 3.15 - 4.2 - - - - - - - - - - 0.5 1.5 3.15 4.2 - VIL 2.0 4.5...