HD74HC180 Datasheet | Hitachi Semiconductor

Description This universal, monolithic, 9-bit (8 data bits plus 1 parity bit) parity generator/checker features odd/even outputs and control inputs to facilitate operation in either odd or even parity applications. Depending on whether even or odd parity is being generated or checked, the even or odd inputs can be utilized as the parity of 9th-bit input. The wordlength capability is easily expanded by cascading. Features - - - - - High Speed Operation: High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs ∑ of H’s at A Thru H Even Odd Even Odd X X Even H H L L H L Odd L L H H H L Outputs ∑ Even H L L H L H ∑ Odd L H H L L H Pin Arrangement G Inputs H Even Inputs Odd Σ Even Σ Odd GND 1 G 2 3 4 5 6 7 (Top view) H Even Odd Σ Even Σ Odd A F E D C B 14 VCC 13 F 12 E 11 D 10 C 9 8 B A Inputs Outputs Logic Diagram Even Odd A B C Σ Even D E F Σ Odd DC Characteristics Ta = 25°C Item Input voltage Symbol VIH Ta = - 40 to +85°C Max - - - 0.5 1.35 1.8 - - - - - 0.1 0.1 0.1 0.33 0.33 ±1.0 40 µA µA I OL = 4 m A I OL = 5.2 m A Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA V I OH = - 4 m A I OH = - 5.2 m A Vin = VIH or VIL I OL = 20 µA V Vin = VIH or VIL I OH = - 20 µA V Unit V Test Conditions VCC (V) Min Typ Max Min 2.0 4.5 6.0 1.5 - 3.15 - 4.2 - - - - - - - - - - 0.5 1.5 3.15 4.2 - VIL 2.0 4.5 6.0 - 1.8 - 1.9 4.4 5.9 4.13...