HD74HC192 Datasheet | Hitachi Semiconductor

Description The HD74HC192 is a decade counter, and the HD74HC193 is a binary counter. Both counters have two separate clock inputs, an up count input and a down count input. All outputs of the flip-flops are simultaneously triggered on the low to high transition of either clock while the other input is held high. The direction of counting is determined by which input is clocked. These counters may be preset by entering the desired data on the data A, data B, data C, and data D inputs. When the load input is taken low the data is loaded independently of either clock input. This feature allows the counters to be used as divide-by-n counters by modifying the count length with the preset inputs. In addition both counters can also be cleared. This is acplished by inputting a high on the clear input. All 4 internal stages are set to a low level independently of either count input. Both a borrow and carry output are provided to enable cascading of both up and down counting functions. The borrow output produces a negative going pulse when the counter underflows and the carry outputs a pulse when the counter overflows. The counters can be cascaded by connecting the carry and borrow outputs of one device to the count up and count down inputs, respectively, of the next device. Features - High Speed Operation: tpd (Clock Up or Count Down to Q) = 21 ns typ (CL = 50 p F) - High Output Current: Fanout of 10 LSTTL Loads - Wide Operating Voltage: VCC = 2 to 6 V - Low Input Current: 1 µA max - Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) - Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74HC192P HD74HC193P DILP-16 pin PRDP0016AE-B (DP-16FV) - HD74HC192FPEL SOP-16 pin (JEITA) HD74HC193FPEL PRSP0016DH-B (FP-16DAV) EL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Rev.3.00, Jan 31, 2006 page 1 of 13 HD74HC192,...