HD74HC195 Datasheet | Hitachi Semiconductor

Description This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear. This shift register can operate in two modes: Parallel load; shift from QA towards QD. Paralle loading is acplished by applying the four bits of data, and taking the Shift/Load control Input low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the clock input. During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the Shift/Load control input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to perform as a J-K or toggle flip-flop as shown in the function table. Features - - - - - High Speed Operation: tpd (Clock to Q) = 13 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs Shift/ Serial K X X X H L H L Parallel A X a X X X X X B X b X X X X X C X c X X X X X D X d X X X X X Outputs QA L a QA0 QA0 L H QAn QB L b QB0 QA0 QAn QAn QAn QC L c QC0 QBn QBn QBn QBn QD L d QD0 QCn QCn QCn QCn QD H d QD0 QCn QCn QCn QCn Clear Load Clock J L H H H H H H H : L : X : X L H H H H H L X X X X L L H H high level (steady state) low level (steady state) don’t care : transition from low to high level. a, b, c, d : the level of steady-state input at inputs A, B, C or D respectively. QA0, QB0, QC0, QD0 : the level of QA, QB, QC or QD respectively, before the indicated steady-state input conditions were established. QAn, QBn, QCn, QDn : the level of QA, QB, QC or QD respectively before the most recent the clock. transition of Pin Arrangement Clear 1 J 2 Serial Inputs K 3 A 4 B 5 Parallel Inputs C 6 D 7 GND 8 (Top view) J K A B C Clear QA QB QC QD QD 16 VCC 15 QA 14 QB 13 QC 12 QD 11 QD...