HD74HC273 Datasheet | Hitachi Semiconductor

Description This device contains 8 master-slave flip-flops with a mon clock and mon clear. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the clock input. The clear input when low, sets all outputs to a low state. Features - - - - - High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs Clear L H H H H L Clock X D X H L X X Outputs Q L H L No change No change Pin Arrangement Clear 1Q 1D 2D 2Q 3Q 3D 4D 4Q 1 2 3 4 5 6 7 8 9 20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 Clock Clear D CK Clear CK D Clear Clear Clear D CK Clear CK D Clear Clear GND 10 (Top view) Logic Diagram Clock 1D Clear CK Q CK D CL Q 1Q 2D D...