HD74HC283 Datasheet | Hitachi Semiconductor

Description The sun ( ) outputs are provided for each bit and the resultant carry (C4) is obtained from the fourth bit. This adder features full internal look ahead across all four bits. This provides the system designer with partial look-ahead performance at the economy and reduced package count of a ripple-carry implementation. The adder logic, including the carry, is implemented in its true for meaning that the endaround carry can be acplished without the need for logic or level inversion. Features - - - - - High Speed Operation: tpd = 19 ns typ (CL = 50 p F) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Outputs Inputs A1/A3 L H L H L H L H L H L H L H L H B1/B3 L L H H L L H H L L H H L L H H A2/A4 L L L L H H H H L L L L H H H H B2/B4 L L L L L L L L H H H H H H H H When C0 = L/When C2 = L ∑1/∑3 L H H L L H H L L H H L L H H L ∑2/∑4 L L L H H H H L H H H L L L L H C2/C4 L L L L L L L H L L L H H H H H When C0 = H/When C2 = H ∑1/∑3 H L L H H L L H H L L H H L L H ∑1/∑4 L H H H H L L L H L L L L H H H C2/C4 L L L L L H H H L H H H H H H H H : high level L : low level Note: Input conditions at A 1, B1, A2, B2, and C0 are used to determine outputs ∑1 and ∑2 and the value of the internal carry C2. The values at C 2, A3, B3, A4 and B4 are then used to determine outputs ∑3, ∑4 and C4. Pin Arrangement ∑2 B2 A2 ∑1 A1 B1 C0 GND 1 2 3 4 5 6 7 8 B2 A2 ∑1 A1 B1 C0 C4 ∑2 B3 A3 ∑3 A4 B4 ∑4 16 VCC 15 B3 14 A3 13 ∑3 12 A4 11 B4 10 ∑4 9 C4 (Top view) Block Diagram C4 B4 A4 ∑4 B3 A3 ∑3 B2 A2 ∑2 B1 A1 C0 ∑1 DC Characteristics Ta = 25°C Item Input voltage Symbol VIH Ta = - 40 to +85°C Max - - - 0.5 1.35 1.8 - - - - - 0.1 0.1 0.1 0.33 0.33 ±1.0 40 µA µA I OL = 4 m A I OL = 5.2 m A Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA V I OH = - 4 m A I OH = - 5.2 m A Vin = VIH or VIL I...