HD74HC299
HD74HC299 is 8-bit Universal Shift/Storage Register (with 3-state outputs) manufactured by Hitachi Semiconductor.
Description
The HD74HC299 features multiplexed inputs/outputs to achieve full 8-bit data handling in a single 20-pin package. Due to the large output drive capability and 3-state feature
, this device is ideally suited for interfacing with bus lines in a bus oriented system. Two function select inputs and two output control inputs are used to choose the mode of operation as listed in the function table. Synchronous parallel loading is acplished by taking both function select lines S0 and S 1 high. This places the 3-state outputs in a high impedance state, which permits data applied to the input/output lines to be clocked into the register. Reading out of the register can be done while the outputs are enabled in any mode. A direct overriding clear input is provided to clear the register whether the outputs are enabled or disabled.
Features
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- High Speed Operation High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
Function Table
Inputs Function Select Mode Clear Clear L L Hold H H Shift Right Shift Left Load H H H H H S1 X L L X L L H H H S0 L X L X H H L L H Output Control G1† G2† L L L L L L L L X L L L L L L L L X Serial Inputs/Outputs Outputs QH’ L L QH0 QH0 QGn QGn H L h
Clock SL SR A/QA B/QB C/QC D/QD E/QE F/QF G/Q G H/QH QA’ X X X L X X X X X X H L X X X X X H L X X X L L QA0 QA0 H L QBn QBn a L L QB0 QB0 QAn QAn QCn QCn b L L QC0 QC0 QBn QBn QDn QDn c L L QD0 QD0 QCn QCn QEn QEn d L L QE0 QE0 QDn QDn QFn QFn e L L QF0 QF0 QEn QEn QGn QGn f L L QG0 QG0 QFn QFn QHn QHn g L L QH0 QH0 QGn QGn H L h L L QA0 QA0 H L QBn QBn a
Notes: 1. a to h; the level of steady-state input at inputs A through H, respectively. These data are loaded into the flip-flop outputs are isolated from the input/output terminals. 2. QA0 to Q H0; the level of QA through QH , respectively, before the indicated steady-state input conditions were...